Flash memory stores data in arrays of memory elements, or cells, formed from floating-gate transistors. NAND flash memory devices return previously stored data by reading a set of bits from individual cells in an array. The time required to erase data from a cell is typically longer than the time required to write data to a cell and typically much longer than the time required to read data from a cell. As sizes for memory elements continue to decrease, erase times and write times continue to increase at a faster rate than read times.
Read operations typically occur at small sets of memory cells, program operations typically occur in the same or larger blocks of multiple memory cells than read operations, and erase operations typically occur at even larger blocks of memory cells. Many flash memory devices are designed to keep read times as low as possible to allow very fast access to the data stored at the memory cells. Write times are typically longer than read times, but shorter than erase times. In various embodiments, a memory device may include one or more chips, and a chip may include one or more memory arrays of memory cells. While an erase operation is being performed for a given cell, other access to the chip on which the cell is located is blocked, including reading data stored at other cells on the same chip or writing data to a block of cells on the same chip. As a result, an application requesting access to a given cell or group of cells for a read operation, a write operation or other operation associated with a memory access request may not be able perform the read/write operation for a significantly long period of time if an erase operation is being performed at the chip on which the given cell is located than if an operation associated with a memory access request is performed automatically upon receipt of the access request.
Throughout the description, similar reference numbers may be used to identify similar elements.